1. Field of the Invention
The present invention relates to an ATM (Asynchronous Transfer Mode) exchange which is provided with a function of exchanging ATM cells.
2. Description of the Prior Art
There has been widely used an ATM exchange that exchanges cells which are fixed-length packets. To exchange the cells, the ATM exchange requires a buffer memory for temporally storing them. Concerning the arrangement and number of the buffer memory, there have been proposed a variety of exchanging methods. Several exchanging methods have been discussed in the following references: (1) "Development of a high-speed ATM exchange system", NTT R&D Vol. 95 No. 10 p. 839-846; and (2) "Method of configuring 160 Gigabit/s ATM exchange with a switch changing a link-speed" SSE 93-69, IN 93-76, CS 93-92 (1993-10).
More definitely, this invention relates to an output buffer type ATM exchange. Hereinafter, the output buffer type ATM exchange will be discussed first. An explanation of an ATM exchange with multiple steps (e.g., an ATM exchange with three steps shown in FIG. 12), which has some drawbacks in contrast with the output buffer type ATM exchange, will follow in order to clarify advantages of the output buffer type ATM exchange, which will proceed focusing on the disadvantages of the ATM exchange with multiple steps.
To summarize the following discussion, the conventional output buffer type ATM exchange shown in FIG. 11(a) has solved the disadvantages of the ATM exchange with multiple steps shown in FIG. 12, that is to say, cell collisions. In the conventional output buffer type ATM exchange in FIG. 11(a), the cells on the common bus 1205 are required to run at extremely high speed, which gives some difficulties, such as limitation on selecting devices, in designing the output buffer type ATM exchange. Therefore, the output buffer type ATM exchange according to this invention removes such difficulties. To attain the object, the principal architecture of the output buffer type ATM exchange in accordance with this invention is as follows: as shown in FIG. 1, the cells output from "one" input unit are distributed or divided into "a plurality of" output units. Furthermore, the present invention employs parallel expansion, which increases the number of the lines on which the cells runs. The parallel expansion allows the cells to run at low speed.
Hereinbelow, a conventional output buffer type ATM exchange will be explained, as an example of exchanging methods with reference to FIG. 11, which shows n by n output buffer type ATM exchange (n denotes the number of input lines and output lines). As shown in FIG. 11(a), each of the input cells 1200-1 to 1200-n are fed into the respective input cell processors 1200-1 to 1200-n via the input line 1201-1 to 1201-n. The input cell processors 1202-1 to 1202-n each make the input cells 1200-1 to 1200-n be in phase, and implement bit expansion thereon, thus outputting the cells which have experienced the bit expansion, to the cell multiplexer 1204 via the lines 1203-1 to 1203-n. The cell multiplexer 1204 performs time division multiplex on the cells, thereby delivering the cells which have undergone the time division multiplex, to the output buffers 1206-1 to 1206-n via the common bus 1205.
In FIG. 11(b), each of the output buffers 1206-1 to 1206-n incorporates the destination reference unit 1209 and the buffer memory 1210. The destination reference unit 1209 identifies the cells on the common bus 1205, to write only the cells directed to the respective buffer memory 1210 therein, whereby each buffer memory 1210 stores the cells directed thereto with the other cells not stored therein.
With respect to the length of the cells, the ITU-T recommendation and the ATM forum defines 53 byte. In most ATM exchanges, at the head of the 53 byte cell is added one byte, which is destination information designating the destination of the output buffer, whereby the 54 byte cell is exchanged. In FIG. 11(a), the length of the cells 1200-1 to 1200-n is 54 byte.
FIG. 11(c) shows the format of the 53 byte cell 1300, which is defined in the ITU-T recommendation and the ATM forum, while showing the format of the 54 byte cell 1301, which has one added byte 1302. In case of the 54 byte cell, the output buffers 1206-1 to 1206-n are necessarily larger, as compared with those of the 53 byte cell 1300. In addition, since the throughput a cell unit is larger, memories for speed control of the cells are necessary.
Incidentally, spreading of multimedia communication requires a high speed and large scale ATM exchange. The capacity of current ATM exchanges ranges from 10 Gbps to 20 Gbps, whereas the necessary capacity of the future ATM exchanges is approximately 100 Gbps.
As one of the schemes of developing the large scale and high speed ATM exchange, there has been known a method of connecting a plurality of switches of 10-20 Gbps exchange capacity, as disclosed in the references (1) and (2). An ATM exchange with three steps is illustrated in FIG. 12. This ATM switch comprises the unit switches 1420 to 1450 at the first step, the unit switches 1421 to 1451 at the second step, and the unit switches 1422 to 1452 at the third step. Here, the unit switch 1420, for example, accommodates input lines 1400-1 to 1400-m. Similarly, the other unit switches 1430, 1440, and 1450 accommodate the input lines 1401-1 to 1401-m, 1402-1 to 1402-m, and 1403-1 to 1403-m, respectively. On the contrary, at the third step, for example, the unit switch 1422 accommodates the output lines 1404-1 to 1404-m. Similarly, the other unit switches 1432, 1442, and 1452 accommodate the output lines 1405-1 to 1405-m, 1406-1 to 1406-m, and 1407-1 to 1407-m, respectively. At the second step, the unit switch 1421 is connected to the unit switches 1420 and 1430 via the respective lines 1411 and 1412, while being connected to the unit switches 1422 and 1432 via the respective lines 1413 and 1414. The other unit switches 1431, 1441, and 1451 are connected likewise. The ATM exchange has some problems as follows.
(1) The throughput in a link, or between a unit switch and the following unit switch, must be fast. For example, assuming that the throughput of each input line is V, the throughput of each link is m.times.V. More specifically, provided that the throughput of each of the input lines is 155.52 Mbps, and the number thereof is eight, the throughput of the link is approximately 1.2 Gbps. This means that a unit switch must have increased throughput, or operating frequency, with an increase in the number of the input lines and throughput thereof. Accordingly, the unit switch must write such fast cells therein.
With respect to devices, in comparison with ECL (Emitter Coupled Logic) and TTL (Transistor transistor Logic), CMOS (Complementary Metal-Oxide-Semiconductor) generally favors large scale integration of the ATM switch, which is advantageous in manufacturing and cost. However, CMOS does not enable the integrated ATM switch to operate beyond 150 MHz, and also imposes several restrictions on circuit designing relevant to delay and layout.
Furthermore, concerning the memory, it is difficult to store large numbers of cells therein at extremely high speed, for example, 150 MHz. Also, the power consumption of the memory increases with an increase of the operating frequency thereof. Hence, it is difficult to employ ECL and TTL in large scale integration of the memory in lieu of the CMOS in terms of operating speed and power consumption.
(2) In order to reduce the throughput of the links, there have been proposed a method of making each link in parallel and another method of increasing the number of the links between the unit switches. These methods, however, may increase the amount of wiring among the unit switches. For example, providing that each unit switch is integrated in a LSI and the LSIs are mounted on a printed wiring board, many wirings among the LSIs may be troublesome. In addition, crosstalk among the wirings and delay of the cells deteriorate with further high operation speed of the links.
Increasing the number of the links allows the unit switches to select the links more freely, which appears to avoid the above collisions. This increases the number of the paths including a plurality of links (e.g., the paths 1408, 1409 and 1410) through which each cell can pass. However, the increase of the paths makes it difficult for each unit switch to judge which of the paths is selected. Furthermore, it is difficult to configure an algorithm for selecting an appropriate path with no cell collision, and if possible, this leads to increasing of the hardware.
(3) There may occur collisions of the cells at the output points of the unit switches of the second step and other following switches. More definitely, assuming that the cells through the input line 1400-1 arrive at the output line 1406-1 while the cells through the input line 1402-1 arrive at the output line 1406-1, the former cells advances along the path 1408 and the latter cells advances along the path 1409. If both cells are fed in the unit switches 1420 and 1440, those cells collide with each other at the output point 1415 of the unit switch 1431 or at the buffer memory therein. Similarly, the cells through the input line 1403-m advance along the path 1410, whereby another collision may arise at the output point 1416 of the unit switch 1442 or the buffer memory thereof. Therefore, cascading a plurality of unit switches requires avoiding such collisions of the cells, which burdens the hardware of the unit switches with a large algorithm for avoidance.
(4) In case of cascading of a plurality of unit switches, there is required a trigger signal from a following unit switch to a preceding unit switch, wherein the control signal instructs the preceding unit switch to output the cells therefrom. Consequently, this further increases the number of wirings between neighboring unit switches. For example, in case of transferring the cells between the unit switch 1420 and the unit switch 1421 via the link 1411, the control signal 1417 originated by the unit switch 1421 serves to request the unit switch 1420 to output the cells to the unit switch 1421.
On the contrary, to cascading a plurality of unit switches, a single switch, such as an output buffer type switch or a common buffer type switch, appear to be preferable. However, these single switches requires multiplexing the input cells. Accordingly, this necessitates high speed operation in transferring and writing.